Low power text compression for Huffman coding using Altera FPGA with power management controller

Huffman coding is very important technique in information theory. It is the process of encoding data using fewer bits than an uncompressed data. Furthermore, Clock gating and frequency scaling are efficient techniques for reducing power consumption in sequential design. It saves more power by partitioning the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. This paper aims to design and implementation of Huffman coding based on binary tree using FPGA (Field Programmable Gate Arrays), and proposing a novel method of clock gating and frequency scaling to achieve low power consumption and reliability of design. The proposed Huffman was achieved 47.95% saving percentage in data size. While, reduce power consumption up to 52.52% comparing to traditional design. Huffman design was implemented by using ASIC and FPGA design methodologies. In order to implement the encoder and decoder architectures, 130 nm standard cell technology libraries were used for ASIC implementation. The simulations are carried out by using Modelsim tool. The architecture of coding and decoding process has been created using Verilog HDL language. Quartus II 11.1 Web Edition (32-Bit). In addition, simulated using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition.