Comparison of the matching circuits for the 65-nm CMOS translation lookaside buffers

This work presents the analysis of power consumptions of the translation lookaside buffer (TLB) registers with two types of matching circuits. One of the registers is based on the upset-hardened STG DICE cells and matching circuit with combinational logic. It is shown, that power consumption of the register with combinational logic in search operation strongly depends on input data of TLB. Minimum and maximum values of power consumption differs by more than 70 times. The other register is based on the matching circuit with match line and the same upset-hardened elements of matching. In search operation, matching circuit with match line has only two transistors, which are sensitive to single nuclear particle impact. Parameters of power consumption for registers with different matching circuits were simulated. Analysis showed, that average power consumptions of matching circuit with match line and matching circuit with combinational logic are practically the same, but maximum power consumption of matching circuit with match line is 45% lower.