Design and simulation of the CMOS RS logical elements with spacing between transistor groups for minimization of single-event upsets

The logical sequential element - RS trigger with spacing transistor groups (STG RS trigger) - was designed and TCAD simulated on the bulk 65-nm CMOS design rule. The effect of single-event upsets under impacts of single nuclear particles on this CMOS logical element was minimized by dividing the transistors of the RS trigger into two special double groups and spacing in between these groups. The topologies of logical elements with interleaving groups of the adjacent RS triggers were designed for the 65-nm CMOS translation lookaside buffers.