TCAD simulation of the 65-nm CMOS logical elements of the decoders with single-event transients compensation

Logical elements with single-event compensations were designed and simulated on the bulk 65-nm CMOS design rule. The effects of single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the co-location in the common group the compensation transistors together with the transistors, which can be affected by single nuclear particle. The combinational logical elements with the proposed layout of the topological single-event compensation were designed to the decoders of matching for the translation lookaside buffers and the decoders to the static RAM.