Research and implementation of hardware algorithms for multiplying binary numbers

The structures of matrix and tree-like multipliers of binary numbers were reviewed and their system characteristics were determined. The internal structure of incomplete one-bit adder and pyramidal adder has been proposed, which allowed reducing the number of equipment in the investigated multiplier structures at 1.7 times and increasing the speed by 1.8 times. Realization of those multipliers and their synthesis was made on FPGA of Xilinx Company. A comparative analysis of the obtained results was made, which made it possible for a designer to choose the optimal structure of the multiplier to accomplish the task of hardware multiplying of binary numbers with given system characteristics.