Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory

String read current (I
_read
) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated I
_read
with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness (T
_Si
), using TCAD. We find that under a critical value of GS, I
_read
decreases with increase in T
_Si
. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which I
_read
is independent of TSi, which is desirable to minimize the deviations in I
_read
arising from TSi variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that I
_read
increases significantly by limiting the polysilicon channel grain boundary trap concentration under 1012 cm
^-2
. The results presented in this paper are crucial for optimizing I
_read
and program/erase threshold voltage(VT) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance.