Mixer-based parallel frequency generation in 65 nm CMOS for FBMC transmitters

This paper presents an equidistant frequency synthesizer approach for filter-bank multicarrier (FBMC) transmitters with a targeted bandwidth of 2 GHz. The realisation of such high bandwidths is a bottleneck concerning extreme high sampling speed. However, the sampling rate can be reduced through the parallelisation in the FBMC transmitter. Nevertheless, the FBMC transmitter requires multiple subchannels with a constant frequency offset. The main approach of the mixer-based topology is to generate the equidistantly spaced frequency sources. The circuit implementation utilizes a mixer-based technique which is feasible for generating 16 equidistantly spaced intermediate frequency (IF) signals in the range of 4 to 6 GHz with a constant frequency offset of 125 MHz. Thereby, a single reference signal at 5 GHz is used. The technique enables a minimum SFDR of around 45 dB and a great reduction of power consumption. The results are proven by schematic and parasitic extracted post layout simulations using a TSMC 65 nm CMOS technology.