1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time

In this paper, a single transistor (1-T) capacitorless DRAM using laterally bandgap engineered Si-Si:C heterostructure bipolar I-MOS is investigated using 2-D calibrated simulations. The proposed device features a high-K gate dielectric, a metal gate, and an epitaxially grown Si0.99C0.01 source/drain regions. Due to lattice mismatch between the Si:C source/drain and the Si channel and resultant strain effect, the proposed 1-T capacitorless DRAM memory cell exhibits enhanced memory characteristics, particularly the sensing margin and the retention time. The proposed 1-T capacitorless DRAM exhibits a sensing margin of the order of ~1.5 μA/μm and ~2.0 μA/μm for the temperatures T = 300 K and T = 358 K, respectively. Also, the proposed 1-T capacitorless DRAM memory cell shows a retention time of ~1.68 s and ~845 ms for T = 300 K and T = 358 K, respectively. Therefore, the proposed 1-T capacitorless memory has a greater potential to replace existing 1-T capacitorless DRAM memory.