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Journals & Magazines >IEEE Design & Test >Volume: 35 Issue: 5

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis

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Pietro Fezzardi; Fabrizio Ferrandi; Christian Pilato
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Abstract:

This article presents an automated approach for detecting system- level bugs in SoC designs that are composed of many IP blocks, without exposing sensitive information. T...Show More

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Abstract:

This article presents an automated approach for detecting system- level bugs in SoC designs that are composed of many IP blocks, without exposing sensitive information. The approach leverages high-level synthesis techniques. —Binoy Ravindran, Virginia Tech
Published in: IEEE Design & Test ( Volume: 35, Issue: 5, October 2018)
Page(s): 54 - 62
Date of Publication: 06 April 2018

ISSN Information:

DOI: 10.1109/MDAT.2018.2824121
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