Modeling of NBTI Kinetics in RMG Si and SiGe FinFETs, Part-I: DC Stress and Recovery

An ultrafast (10-μs delay) measurement technique is used to characterize the negative bias temperature instability-induced threshold voltage shift (ΔV
_T
) in replacement metal gate-based high-K metal gate Si and SiGe p-FinFETs. The dc stress-recovery ΔV
_T
time kinetics, voltage acceleration factor (VAF), and temperature activation energy (E
_A
) are compared for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate-stack. A comprehensive physical model framework based on uncorrelated contributions from the generation of interface (ΔV
_IT
) and bulk oxide (ΔV
_OT
) traps and hole trapping in preexisting defects (ΔV
_HT
) is used to explain the measured data. The impact of Ge% and N% on ΔV
_T
, VAF, E
_A
, temperature (T) dependence of VAF, and stress bias (V
_GSTR
) dependence of E
_A
are quantified. The interface trap generation component is independently verified by direct-current I-V(DCIV) measurements.