Modeling of DDR5 signaling from jitter sequences to accurate bit error rate (BER)

Intel's signal integrity (SI) analysis for memory in the server segment has neither considered correlated jitter nor handled jitter amplification over channel when performing fast analytical signaling analyses. This inaccuracy is no longer feasible with the intended data rates of DDR5. Here, we propose a DDR5 flow that starts from jitter sequences or histograms and ends with signaling analysis via FastBER that can comprehend jitter amplification over I/O channels regardless of whether Tx jitter is correlated or uncorrelated. The paper contributes results of large scale testing of FastBER signaling in such a scenario and also offers solutions to practical issues like jitter extrapolation and time-margin skew due to setup and hold asymmetry.