Complete Solution-Processed Low-Voltage Hybrid CdS Thin-Film Transistors With Polyvinyl Phenol as a Gate Dielectric

In this letter, we fabricated cadmium sulfide (CdS)-based hybrid thin-film transistors (TFTs) using Poly(vinylphenol) (PVP) as the polymer dielectric gate. The synthesis of PVP crosslinked with trimethoxy propyl silane was made by solution processing, and the films were deposited by a dip-coating technique. The PVP films were cured at 200 °C after deposition, which was the highest temperature for the devices processing. The CdS films were deposited at room temperature using a UV photo-assisted chemical bath deposition technique. These dielectric layers have low leakage current density (10
^-8
A/cm
²
) and a high dielectric constant of 4.7 at 1 kHz. The TFTs exhibited superior performance with a low threshold voltage of 0.3 V, ION/OFF current ratio of 105, subthreshold slope 0.25 V/dec, and a high mobility 36.1 cm
²
V
^-1
s
^-1
at operating voltages less than 3 V.