Expected Failures in 3-D Technology and Related Failure Analysis Challenges

After an introduction to 3-D technology, and through silicon via (TSV)- and stacking options, this paper provides an overview of failures that can be expected in 3-D technology and lists the potential failure analysis (FA) techniques that can be applied to find these failures and the related challenges. Various failure mechanisms and effects that can be expected in TSVs, such as Cu pumping, voids, liner/barrier breakdown, electromigration, mechanical stress impact, Cu diffusion, plasma-induced damage, and the keep-out-zone, are discussed. Also, failures due to backside processing (thinning-induced damage, charging, and Cu exposure) and stacking (misalignment, voids, solder squeeze-out, electrostatic discharge, stress-induced cracking, and delamination) are listed. The importance of mechanical stress and chip–package interaction as a main threat for failures in 3-D technology is highlighted. The FA techniques are not discussed in detail (references are provided). There is a clear need for techniques that can detect failures, such as small (micrometer and submicrometer range) cracks, voids, and delaminated regions (both planar and vertical).