Impact of Variations on Synchronizer Performance: An Experimental Study

Synchronizers play a crucial role in obtaining reliable operation in ASICs with multiple clock domains. In this paper, we study the impact of process variations and technology scaling on synchronizer parameter τ. For this we have carried out metastability measurements on FPGAs manufactured at different technology nodes, 90nm and 28nm. To capture the die-to-die variations we have used 4 FPGA boards for each technology node. For capturing within-die variations, we have implemented synchronizer circuits at 200 different locations for the 28nm FPGA and 50 locations for the 90nm chip and the metastability measurements are simultaneously carried out for all synchronizers. The same experiments are also done to capture propagation delay using ring oscillator setup. From the statistical data obtained, we show that as technology scales, the variations in τ are much more than that in FO4 delays. We also show that MTBF calculations based on average τ can be an under-estimated value, and can lead to more failures than expected.