Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm

In this work, we propose a novel concept of the parasitic-aware design automation for the high-performance analog CMOS circuit design. To achieve this, the concept of the automatic schematic-level circuit design is extended to layout-level using the configurable layouts. The configurable layouts allow consideration of exact parasitic from the beginning of the circuit design process. We designed two-stage operational amplifier at layout-level in 0.13μm CMOS technology using the proposed concept. The circuit was designed at layout-level with 0% average design error, satisfying all the specifications. The average design time was only 107.8 minutes. Further, we designed operational amplifier at schematic-level, where exact value of the layout-parasitics is not possible to consider, the design error was 0%. However, the post-layout simulation of this optimized schematic indicated the average design error of 6.46%. We also demonstrated the parasitic-aware automatic design of the operational amplifier considering process and temperature variations. The obtained results show the effectiveness of the proposed concept for designing high-performance analog circuits.