Abstract:
The inability to sense the transitions in the input by conventional phase frequency detector (PFD) during the reset operation leads to blind zone, which reduces the acqui...Show MoreMetadata
Abstract:
The inability to sense the transitions in the input by conventional phase frequency detector (PFD) during the reset operation leads to blind zone, which reduces the acquisition speed and the detection range. The pull down network in proposed design is modified so as to eliminate the reset pulse for phase difference beyond the dead zone in order to have a full detection range and less cycle slippage. As the design gives the right polarity for phase differences close to ±2π, the acquisition time is reduced substantially. The Transfer characteristic of the PFD manifests an identical response. The PFD design is implemented in 180nm CMOS technology and consumes 1.36mW at an operating frequency of 1GHz.
Published in: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
Date of Conference: 06-10 January 2018
Date Added to IEEE Xplore: 29 March 2018
ISBN Information:
Electronic ISSN: 2380-6923