Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs

In this work, we report on a methodology to suppress hysteresis in current-voltage characteristics while retaining steep sub-60 mV/decade switching in n-type Double Gate (DG) Junctionless (JL) transistors. Hysteresis, which occurs due to impact ionization results in two different threshold voltages for forward and reverse gate voltage sweeps, can be effectively suppressed by using independent gate operation. It is shown that hysteresis free drain current with Subthreshold swing (S-swing) ~18 mV/decade can be achieved with a negative back gate (V
_bg
) of -0.9 V. The sub-kT/q S-swing implies negative values of total gate capacitance. The limit on back gate bias is imposed by the extent of Band-to-Band Tunneling (BTBT) which can potentially increase off-current. An optimization methodology is highlighted to suppress off-state BTBT while preserving the effectiveness of impact ionization to achieve sharp hysteresis free drain current transition from off-to-on state.