Silicon on insulator null convention logic based asynchronous circuit design for high performance low power digital systems

Integrated Circuits developed for portable hardware systems are required to operate at ultra-low power supply levels with a considerable speed performance while occupying a relatively small circuit area. These circuit design and optimization constraints impose significant challenges to the whole semiconductor industry. Null Convention Logic based approach has evolved to a prominent clock-less circuit design and optimization technique due to its easiness and readiness in circuit design, implementation, and optimization with Electronic Design Automation tool support. This paper proposes and examines a novel Null Convention Logic gate architecture implemented in Fully-Depleted Silicon on Insulator 28 nanometer technology node targeting mobile systems. The newly-proposed gate architecture has outperformed its conventional NCL static and semi-static CMOS counterparts in terms of power consumption and operational speed and can be dynamically controlled to switch between high speed and ultra-low power low leakage operational modes.