A novel multiplier design for data rendering

Data rendering through an inner product processor is commonly performed in medical imaging and surgical simulators. Multiplication is a fundamental arithmetic operation in inner product processors. Compression of intermediate results involves many computations, and defines power and delay limitations of the multiplier. This paper compares compression performance of our newly proposed hybrid-ABACUS multiplier against standard Wallace tree and recently proposed hybrid Wallace tree, using Dual-Pass Logic design style in 180nm CMOS technology for all. A notable distinction of our design is that our hybrid approach is not limited to the use of counters alone. Wider saturated counters are intermixed with saturated compressors for global optimization of delay and power dissipation. New evaluation criteria have also been introduced as part of the comparison to capture key attributes of the inner product processor. Circuit simulation results show that hybrid-ABACUS design has 9.6% better power delay product or PDP and 20.3% better energy delay product or EDP in comparison with standard Wallace tree approach. In addition, our proposed design yields 37.2% and 55.8% improved PDP and EDP respectively, compared to hybrid Wallace tree, if ripple carry adder is used at the final addition stage. These results improve further if a carry look-ahead adder is used at the final stage.