Wireless powering of mm-scale fully-on-chip neural interfaces

This paper presents guidelines for the design and optimization of on-chip coils used for wirelessly-powered mm-scale neural implants. Since available real estate is limited, on-chip coil design involves managing difficult trade-offs between the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high power transfer efficiency. To illustrate the design optimization procedure, a 3 × 3 mm
²
on-chip coil is designed, and measurement results reveal a 3.82 % power transfer efficiency for a 1.6 kΩ load that mimics a 100 μW neural interface.