An overview of on-chip cache coherence protocols

Cache coherence protocols have significant impact on the performance of distributed and centralized shared-memory of a multiprocessor, and they are required for maintaining data consistency in a chip-multiprocessor system (CMP). Thus, cache protocols play a major role in improving the performance of multiprocessor systems. Specifically, an efficient cache coherence protocol should ensure the updating of processor data, broadcasting valid data other processors and main memory to prevent the main memory or other processors from loading invalid values. To address this issue of efficiency in maintaining cache coherency, several contribution, such as using invalidation-based protocols with a write through cache coherence, have been made over the past years. This paper presents an overview of emerging cache coherence protocols which aim at improving the performance of CMPs. Furthermore, an example of using an invalidation-based protocol with a write through for solving cache's coherency is provided.