Developing and debugging FPGA applications in hardware with JHDL

JHDL is a Java-based suite of design tools developed at Brigham Young University to aid in the design and development of high-performance FPGA applications. The suite consists of a set of JHDL circuit libraries, simulator, schematic generator, hardware debugger and other tools that can be used to design, develop and debug designs. JHDL is a unique design tool that unifies simulation and hardware execution into a single environment. Designers can easily select either simulation or execution and all of the circuit verification and visualization tools are fully usable whether in simulation or hardware execution mode. Because of its unified simulation/execution design environment, JHDL is the first tool that directly supports symbolic debugging of a user design in the original design context while the design is actually executing in FPGA hardware. JHDL allows designers to exploit the immediate availability of FPGA hardware making it possible to test and symbolically debug designs at hardware speeds that run several orders of magnitude faster than simulation. JHDL also supports end-to-end application development of the user circuitry including any control code and any user interface software including graphical user interfaces (GUIs). User circuitry is designed using JHDL libraries while control software and user interface software is written using standard Java libraries such as Swing, for example. This paper gives an overview of the JHDL tool suite and presents a tutorial on JHDL syntax.