Circuit-Level Technique to Design Variation- and Noise-Aware Reliable Dynamic Logic Gates

In this paper, a novel approach to decrease the delay variations in dynamic logic topology is proposed. The proposed method is based on extending the Schmitt trigger characteristics to dynamic gates. A simple model of the proposed technique is derived to accurately approximate the extent to which variations in delay due to process, voltage, and temperature (PVT) fluctuations can be mitigated. Reliability analyses with PVT variations have been extensively performed on NAND/NOR logic implementations of the proposed methodology. Analyses reveal about 50% reduction in delay variability, with additional improvement in noise margin at an expense of slight increase in delay. The proposed approach was assessed by Monte Carlo simulations in the SPICE environment, and the analysis results support the theoretical proposal.