Digital synthetic ripple modulation technique for DC-DC converter by using FPGA controller: Modulation technique for synchronus buck converter by using FPGA controller

Voltage regulator modules (VRMs) powering the microprocessors are required to fulfill the stringent specifications on the core voltage ripple and voltage regulation. These specifications are accomplished by the microprocessor's higher di/dt requirements and the need to operate at a lower level of supply voltage for reduced power consumption. The VRMs resort to multi-phase pulse width modulation (PWM) control scheme to the high current demands and provide balanced load current sharing. The control schemes also involve a combination of voltage-mode and current-mode or current-mode and hysteretic-mode control. Thus, these schemes add to the cost and complexity of the VRM. The digital SRM (DSRM) scheme employed in the control of the buck converter also involves a novel method for deriving the duty ratio, with the generated time-intervals inversely related to a sampled converter parameter. The duty ratio generation scheme is based on a unique scaling process and eliminates the need for a high clock frequency. The modulation scheme utilizes the sampled inductor voltage, which is scaled and successively accumulated to generate the synthetic ripple. The error in the output voltage when compared to a reference or command voltage is added to the synthetic ripple resulting in the carrier signal for PWM operation. The carrier signal is modulated between the hysteretic limits of output, resulting in the required duty ratio. Since the carrier signal involved in the PWM signal generation is derived from the converter parameters in the SRM scheme, natural input feed-forward control is also attained. This enables better rejection of line input disturbances.