Heterogeneous and homogeneous package integration technologies at device and system levels

Moore's law scaling has been the primary focus in the last 60 years towards System-On-Chip. This has resulted in an industry-driven, device-level integration to a 50 billion transistor chip, incorporating progressively more and more functions in a single die, along with cost reduction from node to node. However, as Moore's law approaches limits in combined scaling and cost reduction, there is an unparalleled opportunity for package integration to enable better devices in the short term and to enable better systems in the long term, both by homogeneous and heterogeneous integrations. This paper presents the package integration evolution to the current approaches at device and system-levels. It then presents Georgia Tech's vision in advancing package integration at device-level by extending the on-going 2D, 2.5D, and 3D architectures as well as proposing an entirely new approach to materials, processes, and architectures at both device and system-levels. Both are enabled by ultra-thin packaging with TSV-like through vias in the passive substrates rather than in the logic ICs. At system level, it proposes and develops a 3D architecture that combines both package and system functions into an ultra-miniaturized, highly integrated, and highly reliable system package with ultra-short and ultra-high bandwidth interconnections with ultra-high reliability.