Design and analysis of multiple port memory architecture for low power applications

As flash memory technology scales down the 20 nm and below, data reliability becomes a major design concern for storage systems. A novel integrated approach is proposed for chip architecture. The conventional architecture suffers from read disturbance during high amount of power consumption. A read disturb error occurs which causes data loss to a page. To overcome the problem of read disturbance parallel processing multi input multi output round robin algorithm is proposed and also adopted clock gating technique in the architecture. The proposed round robin algorithm is used for the multiple processing of inputs and outputs. It can reduce the read disturbance and consumes low power. The simulations are implemented on the Xilinx ISE 14.7 tool. By using round robin algorithm and clock gating together increase the performance and reduce the area, delay and power consumption.