Pipelined VLSI architecture of the Viterbi decoder for IMT-2000

An improved VLSI architecture for the high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the add-compare-select unit (ACSU), removed the minimum metric selection logic and exploited constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discuss unnecessity of minimum metric selection logic in the point of truncation effects. Simulation results demonstrate that if the traceback depth is set long enough, the arbitrary state decoding can be used without much disadvantage over the best state decoding. The survival memory unit (SMU) pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the 2 registers and multiplexer, we made one-stage pipeline cell and by cascading them, the traceback operation without LIFO or some complex memory controller can be achieved with a latency of only 2T.