Reducing buffer requirement for VC-merge capable ATM switches

The multiprotocol label switching (MPLS) paradigm of integrating layer-3 routing with layer-2 switching has been proposed as a viable alternative to today's router architecture. When MPLS is applied to the design of large core routers, label merging is required in order to support scalability. In this paper, we assume that ATM is the layer-2 switching mechanism. We investigate the impact of VC merging on buffer requirement. Results indicate that buffer requirement of VC merging can be excessive when compared to non-VC merging. This is in contrast to previous findings. We propose three schemes to significantly reduce the buffer requirement for VC merging.