An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance

RRAM is an attractive and low-cost memory structure for embedded applications due to the simplicity of the RRAM element (RE) and its compatibility with a logic process. A RRAM bit cell (Fig. 30.1.1) consists of an NMOS select transistor and a bipolar RE, which consists of a bottom electrode (BE), a transition metal-oxide file (Hi-K), a metal capping layer and a top electrode (TE). The memory cell operates as a 3-terminal device, including bit-line (BL), source-line (SL) and word-line (WL). BL is connecting to TE, SL is connecting to the source node of the select transistor and word-line (WL) is connecting to the gate of the select transistor. A common SL (CSL) architecture is adopted in this work. CSL allows two or more columns to share one source line. So that the column mux number for SL can be reduced, therefore macro area can be saved. In addition, SL can be implemented with a wider metal track due to the reduced SL count. Therefore, the SL resistance also can be reduced. However, a CSL architecture will result in a larger parasitic capacitance on SL. This paper presents an SL precharge scheme to deal this increased capacitance when reading from the CSL.