A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and −249dB FOM

Multiplying delay-locked loops (MDLL) and injection-locked clock multipliers (ILCM) have shown improved jitter performance in recent years [1-5], but their PLL-based frequency-tracking loops (FTLs) for securing performance against frequency and PVT variations are area and power hungry. In [1], the frequency (F
OUT
) is tracked by a replica-delay cell of the VCO, such that the intrinsic phase information is preserved under reference injection (REF-INJ). Regrettably an analog FTL is susceptible to noise and mismatch from the charge pump, demanding more area (loop filter: 0.01mm
²
) and power (charge pump: 0.8mW) to limit the in-band jitter deterioration.