Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration

We are proposing a double gate junction-less device with a processing temperature compatible with state-of-the-art dense low k dielectric back-end of line copper process. The thermal stability of the back-end of line process was studied, showing no degradation for an anneal temperature up to 500°C 1h. Using wafer bonding, a crystalline silicon layer can be transferred onto a carrier wafer followed by top device processing at low temperature with a gate first approach as well as direct W contacts with Ti/TiN barrier layer. To avoid dopant activation using high temperature anneal (spike), junction-less devices are used, where the uniform channel dopant implantation and activation can be done prior to the layer transfer.