Sense amplifier based high speed flip-flop design for advanced sub-micron FinFET standard cell library

A novel high-speed sense-amplifier based flip-flop is presented in this paper. The proposed flip-flop design has improved D2Q delay and a glitch-less output. An in-depth analysis of sense-amplifier stacking order is presented and the proposed sense-amplifier design exploit multiple stacking orders of the clocked devices, input and feedback transistor and show approximately 25% overall advantage in performance of the flop as compared to the conventional variant of a flip-flop. Simulation results were obtained for sub-micron FinFET technology using industry standard production characterization setup. Monte Carlo stress checks were performed on the proposed designs to ensure bug-free operation and high-yield at the time of fabrication.