A 45nm ultra-low power operational amplifier with high gain and high CMRR

This paper presents an ultra-low power operational amplifier (opamp) with high gain and high common-mode rejection ratio (CMRR) in 45nm CMOS technology. It uses a bulk-driven differential pair in the input stage to facilitate low voltage design and to achieve a high input common-mode range (ICMR). In addition, the design employs an auxiliary differential pair that utilizes dynamic threshold MOS (DTMOS) technique to enhance the effective transconductance and hence achieves high gain and high unity-gain bandwidth (UGB). All the transistors are biased to operate in subthreshold region in order to minimize power consumption. Simulation with Cadence Virtuoso for 350 mV of supply and a load capacitance of 1 pF, yields a DC gain of 77.03 dB, CMRR of 130.8 dB, UGB of 456.9 kHz and a phase margin of 82.47° for a power consumption of 21.75 nW.