Optimization of wire-length and block rearrangements for a modern IC placement using evolutionary techniques

The block Re-arrangements of standard cell IC plays a vital role in allocating white spaces between the blocks. That white spaces can be occupied by placing a Through Silicon via (TSVs), which is used for the interconnection between the blocks as well as between the layers and also wire-length can be optimized to certain extent. In this paper the wirelength and whitespace is optimized to 10% and 14% respectively. This result has been compared with the two algorithms. First is Differential Evolution algorithms and second, is the genetic algorithm with the inputs of IBM-PLACE benchmarks circuits.