Power Supply Noise Reduction of Multicore CPU by Staggering Current and Variable Clock Frequency

Central processing unit (CPU) for any computer generally operates at constant power supply voltage. Normally in product specification, this power supply voltage has tolerance margin close to ±5%. It is shown in the previous works that for every millivolt drop in power supply voltage, the operation frequency of a chip reduces by about 2 MHz. This voltage drop occurs when CPU starts drawing current from the power supply. It is desirable to maintain the supply voltage within the specification of allowed voltage fluctuations so that the CPU can run at the target operating frequency, for a given package inductance and die decoupling capacitance. In this paper, power supply noise reduction method for multicore CPU in a given silicon chip has been considered. The concept of variable frequency has been applied on every core to minimize the noise by changing the current ramp of a multicore system. This reduces the dI/dt, and therefore for fixed package inductance and die decoupling capacitance, the power supply noise reduces. In this paper, four-core CPU has been taken and also shown the reduction of noise by changing the current ramp using variable clock frequency on each core and also by staggering the time when each core will start clocking.