Design and implementation of different types of full adders in ALU and leakage minimization

In the era of nanotechnology, leakage current, active power, delay, area bear an important metric for design and analysis of complex arithmetic logic circuits. In this paper major work has been done in determining leakage current, power and their analysis. Different full adders such as 28T, 14T, 11T and 10T have been designed and implemented in ALU. The 10T full adder has been designed by using optimal sleep transistors in reverse bias which can minimize leakage power as compared to other full adders. A comparison has been made among all these adders and the most efficient adder is obtained. We have performed full adder simulations in cadence virtuoso 180nm technology and simulations have been compared for low leakage power. The thesis not only concentrates on the design but also implementation has been done in obtaining the arithmetic logic unit block.