Performance analysis of 16 × 16, 32 × 32, 64 × 64 2-D mesh topologies for network on chip

Network on Chip (NoC) is an up-coming worldview that adapts to the expanding many-sided quality and correspondence prerequisite of future System on Chip (SoC). Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the Mesh topology for 4 × 4 and 8 × 8,16 × 16, 32 × 32, 64 × 64 nodes for varying packets size (0.1 and 16 000 kB), queue size (5-200), link bandwidth (10-200 Mbps), link propagation delay (10-200 ms), over CBR (5 and 10 Mbps) and FTP applications. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low (0.512 kB) and high load (64 kB) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to accomplish ideal execution for respective applications of future wireless communications systems is to provide sensor data transmission high-data-rate, quality of service (QoS), low cost, speed of wireless access. Multiple-input multipleoutput (MIMO) wireless technology meet these demands spectral efficiency, and improved link reliability.