Turbo4: a high bit-rate chip for turbo code encoding and decoding

This paper deals with an experimental IC developed for encoding and decoding turbo codes. The chip includes an encoder and a decoding module which performs one iteration of the decoding process. All the necessary interleaving memories and delay-lines are included in the circuit. The encoder is made up of a parallel concatenation of 2 convolutional encoders (constraint length=5) separated by an interleaver (64/spl times/32 matrix). The decoder uses the SOVA technique and a dedicated module achieves the synchronization task as well as a supervision function. Very high level performances can be achieved in 5 iterations: with a QPSK modulation, a BER of 2.E-8 is obtained with Eb/No=2 dB. The turbo4 chip can work in continuous mode up to 54 Mbits/s useful data throughput and is well suited for data flow applications such as video broadcasting. The IC is designed in a 0.25 /spl mu/m CMOS technology and its core size is less than 8 mm/sup 2/.