Binary Counter Based Gated Clock Tree for Integrated CPU Chip

The conventional clock tree, made of some buffers, is prone to large current with the increase in switching clock frequency. Due to the high current peak at the clock edge, the power and ground noise (PGN / PSN) of a CPU chip increases significantly to engender a crucial effect on the circuit performance metrics such as the delay and power dissipation of the entire chip. This current peak also gets increased when numerous signals, driven by the neighboring sources, switch simultaneously. To eliminate the above stated issue, we have come up with a new approach of designing clock tree consisting of a binary counter and an enable signal generator with reset logic. The generated enable signals control the switching of different gates of the clock tree at different time, thereby helps to yield a new current profile by reducing both the current peak and current ramp, the main culprit of power and ground noise. This work of Binary Counter based Gated Clock Tree Circuit (GCTC) is simulated for 90nm CMOS technology using CADENCE Virtuoso platform at a power supply of 1.2Volt and 5 GHz operating frequency. It is observed that the proposed GCTC outsmart the conventional method by mitigating average power, average current, current ramp and PSN by 1.88%, 9.97%, 91.9% and 83.43% respectively.