STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures

Spin Transfer Torque-Magnetic Random Access Memory (STT-MRAM) is one of the most promising alternatives to Static Random Access Memory (SRAM) for integrated memory, owing to high density, low leakage and possibility of high-speed read-write operation. In this work, we explore the advantages of STT-MRAM for a parallel processing application specific integrated circuit (ASIC) architecture of fully connected deep learning network. Low power architectures for deep learning networks have gained significant attention in recent years, owing to their potential for edge computing. For a deep-net, memory read operations for fetching network weights constitute major fraction of total power dissipation. In this work, we show that read-optimized STT-MRAM bit-cells can achieve 80% low power read access power as compared to SRAM, through voltage-mode read operation. Such a read scheme can facilitate low voltage operation, which significantly adds to the energy benefits. Hence, apart from the benefits of area and leakage, low power STT-MRAM can also help in achieving low power read access for memory intensive deep-learning architectures.