Physical implementation of an ASIC-oriented SRAM-based viterbi decoder

Noise plays a key role in data storage and transmission circuits and systems, a threat to data integrity. Hence, it is essential in these circuits to use some form of redundancy with Forward Error Correction (FEC) schemes to prevent data loss or re-transmission, or both. Convolutional coding represents a good trade-off between both performance and encoding/decoding circuit complexity when the Viterbi algorithm is applied. After a review of the decoding algorithm and its architectural design, this paper presents and discusses the physical implementation of a Viterbi decoder hardware accelerator in CMOS 180 nm process. This article exposes fundamental aspects of the physical design, investigating how the SRAM memory IP blocks impacted the overall die floorplan and its detailed routing.