Design of CMOS dynamic logic circuits to improve noise immunity

Dynamic CMOS logic circuits are mostly used in VLSI chips. It provides highest performance compared to different logic families like TTL, ECL. The noise tolerance of dynamic CMOS logic gates can be improved because of its faster speed and compact area than the static logic gates. This paper gives design of 3-input AND gate using feedback keeper and conditional feedback keeper technique. To improve the noise immunity of circuit, the performance of feedback keeper and conditional keeper are optimized. The area, average power, delay and mean noise amplitude of the circuits are reduced. This circuits are designed using 0.25μm process technology and the simulation result is carried out using HSPICE at 1.8V voltage supply at a temperature of 25°C.