Implementation of automatic test pattern generator for asynchronous circuits using SRAM based FPGA

In the asynchronous circuits design method is treated to be a assuring solutions to forth coming challenges of designing of complicated Integrated Circuits. Some of the substantial challenges of asynchronous circuits are the shortage of ample controllability while the test pattern generation, memory sizes and also able to obtain low fault coverage's. The objective is to get feasible test patterns outcomes and high fault coverage using ATPG (Automatic Test Pattern Generation) methodology. In the proposed method test the dbyc and S27 benchmark type of asynchronous circuits for identifying faults using stuck-at-fault models and the testability measurement techniques. The point of controllability and observability measurements are introduced by using the testability measurement tool. In this tool, works depending upon the ATPG techniques and its algorithms. It can be reduced by finding test vectors based on primary inputs and primary outputs of the asynchronous circuits. Test patterns are achieved for the asynchronous benchmark circuits. Simulation results are obtained for asynchronous benchmark circuits using Modelsim, its implementation using SRAM based FPGA, in Xilinx software tool. The results shows comparison of both fault forced and fault free circuit which, demonstrate the ATPG that gives test patterns and higher fault coverage.