System level SEUs propagation analysis via data flow-based reduction and quantitative model checking

Reliability is considered as one of the primary design requirements in embedded systems. Soft errors induced by radiation jeopardize system performance and hence system reliability especially in nowadays technology. CMOS integrated circuits have become more vulnerable to soft errors as transistor size continues shrinking with technology development. Addressing reliability issues due to soft errors at an early stage becomes an essential step to reduce the mitigation cost in the following stages. In this paper, we propose a methodology to analyze soft errors due to Single Event Upsets (SEUs) at the system level. SEUs occurrence and propagation are modeled and analyzed based on Markov decision process and probabilistic model checking. The proposed technique has high scalability by reducing the complexity of the Data Flow Graph (DFG) representation of the system. The proposed technique is proven to provide more accurate results regarding the estimation of the fault propagation rate. FIR filter is used as a case study to evaluate the validity of our approach in providing more accurate fault propagation rate. The DFGs of different orders of different sizes/orders of the FIR-filters are constructed and modeled using PRISM probabilistic model checker. This technique provides an improvement in terms of analysis time with an average speedup of 18.5 times.