Implementation of AES algorithm using VHDL

The Advanced Encryption Standard (AES) postulates a cryptographic procedure approved by FIPS to safeguard data in electronic form. AES algorithm is a symmetric block cipher that can be used for encrypting (encipher) and decrypting (decipher) data. The Advanced Encryption Standard was accepted as an up gradation after the previously used Data Encryption Standard (DES) was found to be weak due to its small key size and technical advances in processor power. Out of the fifteen algorithms in contention Rijndael was selected as the new standard for encryption. Two Belgian inventors, Joan Daemen and Vincent Rijmen collaborated to establish the name of Rijindael. It being a block cipher, its mechanism is on permanent length group of bits, called blocks. An input block of a assured size, usually 128 bits, is taken and an equivalent output block of the same size is produced. A secret key acts as second input of lengths of 128, 192 or 256 bits. Basically AES adopts a substitution-permutation set-up, which concatenates a series of mathematical operations that use substitutions with known values and combination of transformation in a permuted iteration in such a way that each input bit manipulates every output bit. Here we explore the steps in AES and its implementation on FPGA using VHDL. FPGA is the best platform which specializes in fast iterative process using least devices.