An ultra low power fully synthesizable digital phase and frequency detector for ADPLL applications in 55 nm CMOS technology

In this paper, an ultra low power, fully synthesizable digital phase and frequency detector (DPFD) is presented for all digital phase lock loop (ADPLL) applications in bluetooth low energy (BLE) transceiver. The adaptation technique is applied in the fractional feedback loop to achieve highly accurate target frequency of digitally controlled oscillator (DCO). The range extension feature facilitates the DCO to generate stable frequency under severe phase noise. The polarity control for different BLE frequency channels is also incorporated in the proposed design. The external mode for debugging is embedded in the suggested architecture. The proposed DPFD is integrated in an ADPLL for BLE transceiver. The chip is fabricated with TSMC 55 nm CMOS technology. The DPFD occupies a very small area of 1830 μm
²
and it requires only 1.906 K gates for its implementation. The current consumption is upto 40 μA with 1 V power supply and it needs only 40 μW power for its full operation. The measurement and simulation results verify the functional accuracy of the proposed fully synthsizable DPFD architecture.