Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA

RPC-FPGA is a remote procedure call protocol implementation of the Open Network Computing ONC-RPC specification for use in FPGA accelerators. The implementation involves the generation of High-Level Synthesis (HLS) interface stubs to call a hardware procedure and stream the data between the processor and the FPGA. The RPC protocol is extended to accept variable-length arrays with multiple dimensions. This extension is required to support optimizing nested loop transformations on multidimensional arrays stored in the reconfigurable logic. The major benefits of RPC-FPGA are: hardware procedures running on an FPGA accelerator become accessible for any client in the network, multiple hardware procedures run in a truly parallel fashion and the development time of the communication interface between the processor and the FPGA is largely reduced. Using RPC-FPGA a speedup gain of 17 to 20 is demonstrated on a square matrix multiplication of N=4096 with network speeds 100 Mbps and 1 Gbps respectively.