Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study

The increasing number of candidates competing in cryptographic contests has made hardware benchmarking using the traditional Register-Transfer Level (RTL) methodology too inefficient and potentially unfair, especially at the early stages of the competitions. In this paper, we propose supplementing, and eventually replacing, this traditional RTL methodology with the use of High-Level Synthesis (HLS) tools. We apply our proposed HLS-based approach to FPGA benchmarking in the ongoing CAESAR contest, by comparing and ranking 16 authenticated ciphers, including the current standard, AES-GCM, and the primary variants of 13 Round 3 CAESAR candidates. After a careful survey of available HLS tools, we chose Xilinx Vivado HLS as our primary benchmarking tool. Our study has demonstrated high correlation between the rankings of the evaluated algorithms, obtained using both investigated methodologies. In particular, after applying HLS, the algorithm rankings in terms of two major performance metrics — throughput and throughput to area ratio — have either remained unchanged or have been affected only for algorithms with very similar RTL performance.