VHDL generator for a high performance convolutional neural network FPGA-based accelerator

Convolutional Neural Network (CNN) has been proven as a highly accurate and effective algorithm that has been used in a variety of applications such as handwriting digit recognition, visual recognition, and image classification. As a matter of fact, state-of-the-art CNNs are computationally intensive; however, their parallel and modular nature make platforms like FPGAs well suited for the acceleration process. A typical CNN takes a very long development round on FPGAs, hence in this paper, we propose a tool which allows developers, through a configurable user-interface, to automatically generate VHDL code for their desired CNN model. The generated code or architecture is modular, massively parallel, reconfigurable, scalable, fully pipelined, and adaptive to different CNN models. We demonstrate the automatic VHDL generator and its adaptability by implementing a small-scale CNN model “LeNet” and a large-scale one “AlexNet”. The parameters of small scale models are automatically hard-coded as constants (part of the programmable logic) to overcome the memory bottleneck issue. On a Xilinx Virtex-7 running at 200 MHz, the system is capable of processing up to 125k images/s of size 28×28 for LeNet and achieved a peak performance of 611.52 GOP/s and 414 FPS for AlexNet.