Evaluation of the CAESAR hardware API for lightweight implementations

The Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) requires that all hardware implementations of candidate algorithms adhere to the CAESAR Hardware API [1]. The CAESAR Hardware API is supported by a development package which includes VHDL code for universal pre- and post-processors for high-speed and recently also for lightweight implementations. These processors are designed to make a cipher core compliant with the API. However, for lightweight implementations it is generally assumed that having generic pre- and post-processors increases the area consumption over merging their functionality with the cipher cores. In this paper we evaluate the lightweight package through two case studies. First, we verified that the lightweight package has a smaller area footprint than the high-speed package. Second, we show that the overhead of using the generic lightweight pre- and post-processors over integrating their functionality into the cipher core is negligible. As part of these case studies, we have developed the first lightweight implementations of Ketje-Sr, Ascon-128, and Ascon-128a.